WEBINAR: Expand Your Logic About the NXP LPC804 MCU *

Continuing its history of innovation in MCUs, NXP introduces a programmable logic unit (PLU) to the LPC family for the first time with the LPC804 MCU. The Programmable Logic Unit is intended to be used to create small and/or sequential logic networks including simple state machines. To help customer leverage this unique piece of IP on the LPC804 we have develop a simple graphical UI development tool. Join us for this webinar to see how easy it is set up the PLU as we will explore several real-world examples of the challenges many face, but can be overcome with this unique feature.

LPC804 MCUs feature a power optimized core and level shifting options thanks to separate power rails. The peripheral components include a CRC engine, I²C-bus interfaces, up to two USARTs, one SPI interface, and a capacitive touch interface. Timer options include a multi-rate timer, self-wake-up timer, and a general purpose 32-bit counter/timer. The analog peripherals include a 12-bit ADC, an analog comparator, and a separate 10-bit DAC. The controllers also feature function-configurable I/O ports through a switch matrix, an input pattern match engine, programmable logic unit, and up to 30 general-purpose I/O pins.